Sure, that’s one solution. You could also Isle of Dr Moreau your way to a pelican that can use a regular bike. The sky is the limit when you have no scruples.
It is clear from the quality that all vendors of EDA software actively hate their paying customers.
Just wonder - why are EDA tools just now starting to get HiDPI support? I’m pretty sure Altera, Xilinx/AMD, etc haven’t bought HiDPI monitors for their own developers!
The top-level Verilog module and Vivado .xdc file (contains pin mappings, timing constraints, etc) from Gidel for the HawkEye 20G-48. [0] No SDK from Gidel though.
My back burner project for them is to create a PCIe TLP sniffer/MiTM/device emulator by hooking up two together via 10 GbE for relaying TLPs with one of the remaining 10 GbE connection going to a host PC for the sniffed/injected TLPs. The Aria 10 FPGA PCIe hard IP allows for either root or endpoint mode so I “just” need to draw the rest of the owl, avoiding any Quartus IP modules that would make the setup non-transparent.
I’m not sure what using a 10 Gbit link for PCIe will be like with faster devices but fail0verflow got away with TLP proxying with 115200 baud UART. [1]
Vivado, along with expensive adaptors, supports some JTAG dongles that are just FT2232 with an EEPROM that contains USB descriptors that Vivado recognizes and treats as a (some low cost onboard adaptor for Digilent boards, IIRC) supported adapter.
https://gist.github.com/rikka0w0/24b58b54473227502fa0334bbe7...
If you like FT2232, you’ll love the Tigard board that takes a FT2232H and adds level shifters and is basically as tricked out as you can make a FTDI adapter.
https://github.com/tigard-tools/tigard
